The present invention relates to a method for manufacturing electronic devices, having non-volatile memory cells and LV transistors with salicided junctions.
In advanced processes (gate lengths of 0.35 xcexcm or less), the need has recently arisen to integrate EEPROM-type non-volatile memories in high-speed devices that use the technique of saliciding of the diffusions. As is known, this technique is based on the use of a layer of self-aligned silicide (xe2x80x9csalicidexe2x80x9d), which reduces the resistivity of the junctions. The salicide layer (typically of titanium, but also cobalt or another transition metal) is obtained by depositing a titanium layer on the entire surface of the device, and performing a heat treatment which makes the titanium react with the silicon, which is left bare on the junctions and the gate regions, such as to form titanium silicide. Subsequently, the non-reacted titanium (for example that is deposited on oxide regions), is removed by etching with an appropriate solution, which leaves the titanium silicide intact. Thereby, both the gate regions and the junctions have in parallel a layer of silicide with low resistivity (approximately 3-4 xcexa9/square), which makes it possible to reduce the resistance in series at the transistors. The salicide technique is described for example in the article xe2x80x9cApplication of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxide-semiconductor and complementary metal-oxide-semiconductor technologiesxe2x80x9d by R. A. Haken, in J. Vac. Sci. Technol. B, vol 3, No. 6, November/December 1985.
The high voltages necessary for programming non-volatile memories (greater than 16 V) are however incompatible with saliciding of the diffusions of the memory cells, since the breakdown voltage of the salicided junctions is lower than 13 V.
Process flows are thus being designed which permit integration of nonvolatile memory cells and high-speed transistors with saliciding; however this integration is made difficult by the fact that these components have different characteristics, and require different process steps.
The invention thus provides a method for manufacturing non-volatile cells and high-speed transistors, which is simple, and has the lowest possible costs.
According to the present invention, a method is provided for manufacturing electronic devices, such as non-volatile memory cells and LV transistors with salicided junctions. The invention also relates to an electronic device made with the foregoing method.